gpio_intmask
Controls which pins cause interrupts on Port A Data Register inputs.
| Module Instance | Base Address | Register Address |
|---|---|---|
| gpio0 | 0xFF708000 | 0xFF708034 |
| gpio1 | 0xFF709000 | 0xFF709034 |
| gpio2 | 0xFF70A000 | 0xFF70A034 |
Offset: 0x34
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
gpio_intmask RW 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
gpio_intmask RW 0x0 |
|||||||||||||||
gpio_intmask Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 28:0 | gpio_intmask | Controls whether an interrupt on Port A Data Register can generate an interrupt to the interrupt controller by not masking it. The unmasked status can be read as well as the resultant status after masking. Note that only bits[26:0] are implemented for gpio2.
|
RW | 0x0 |