sr

Reports FIFO transfer status, and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt.
Module Instance Base Address Register Address
spis0 0xFFE02000 0xFFE02028
spis1 0xFFE03000 0xFFE03028

Offset: 0x28

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

txe

RO 0x0

rff

RO 0x0

rfne

RO 0x0

tfe

RO 0x1

tfnf

RO 0x1

busy

RO 0x0

sr Fields

Bit Name Description Access Reset
5 txe

Data from the previous transmission is resent on the txd line. This bit is cleared when read.

Value Description
0x0 No Error
0x1 Transmission Error
RO 0x0
4 rff

Reports the status of receive FIFO Full

Value Description
0x0 Receive FIFO is not full
0x1 Receive FIFO is full
RO 0x0
3 rfne

Reports the status of receive FIFO empty.

Value Description
0x0 Receive FIFO is empty
0x1 Receive FIFO is not empty
RO 0x0
2 tfe

Reports the status of transmit FIFO empty. This bit field does not request an interrupt.

Value Description
0x1 Transmit FIFO is empty
0x0 Transmit FIFO is not empty
RO 0x1
1 tfnf

Reports the status of the transmit FIFO.

Value Description
0x0 Transmit FIFO is full
0x1 Transmit FIFO is not full
RO 0x1
0 busy

Reports the status of a serial transfer

Value Description
0x0 SPI Slave is inactive (idle or disabled)
0x1 SPI Slave is actively transferring data
RO 0x0