Power and Clock Gating Register Register Descriptions There is a single register for power and clock gating. It is available in both Host and Device modes. Offset: 0xe00 pcgcctl This register is available in Host and Device modes. The application can use this register to control the core's power-down and clock gating features. Because the CSR module is turned off during power-down, this register is implemented in the AHB Slave BIU module.