doeptsiz14

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00CD0`
`usb1`	`0xFFB40000`	`0xFFB40CD0`

Offset: 0xCD0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`	`rxdpid` `RO 0x0`		`pktcnt` `RW 0x0`										`xfersize` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`xfersize` `RW 0x0`

doeptsiz14 Fields

Bit

Name

Description

Access

Reset

30:29

rxdpid

Applies to isochronous OUT endpoints only.This is the data PID received in the last packet for this endpoint. Use datax. Applies to control OUT Endpoints only. Use packetx. This field specifies the number of back-to-back SETUP data packets the endpoint can receive.

Value	Description
0x0	DATA0
0x1	DATA2 or 1 packet
0x2	DATA1 or 2 packets
0x3	MDATA or 3 packets

RO

0x0

28:19

pktcnt

Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.This field is decremented every time a packet (maximum size or short packet) is read from the RxFIFO.

RW

0x0

18:0

xfersize

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be Set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the RxFIFO.

RW

0x0