doepint1

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00B28
usb1 0xFFB40000 0xFFB40B28

Offset: 0xB28

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

nyetintrpt

RO 0x0

nakintrpt

RO 0x0

bbleerr

RO 0x0

pktdrpsts

RO 0x0

Reserved

bnaintr

RO 0x0

outpkterr

RO 0x0

Reserved

back2backsetup

RO 0x0

stsphsercvd

RO 0x0

outtknepdis

RO 0x0

setup

RO 0x0

ahberr

RO 0x0

epdisbld

RO 0x0

xfercompl

RO 0x0

doepint1 Fields

Bit Name Description Access Reset
14 nyetintrpt

The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Value Description
0x0 No interrupt
0x1 NYET Interrupt
RO 0x0
13 nakintrpt

The core generates this interrupt when a NAK is transmitted or received by the device. In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

Value Description
0x0 No interrupt
0x1 NAK Interrupt
RO 0x0
12 bbleerr

The core generates this interrupt when babble is received for the endpoint.

Value Description
0x0 No interrupt
0x1 BbleErr interrupt
RO 0x0
11 pktdrpsts

This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.

Value Description
0x0 No interrupt
0x1 Packet Drop Status interrupt
RO 0x0
9 bnaintr

This bit is valid only when Scatter/Gather DMA mode is This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done

Value Description
0x0 No interrupt
0x1 BNA interrupt
RO 0x0
8 outpkterr

Applies to OUT endpoints Only This interrupt is asserted when the core detects an overflow or a CRC error for non-Isochronous OUT packet.

Value Description
0x0 No OUT Packet Error
0x1 OUT Packet Error
RO 0x0
6 back2backsetup

Applies to Control OUT endpoints only. This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint. for information about handling this interrupt,

Value Description
0x0 No Back-to-Back SETUP Packets Received
0x1 Back-to-Back SETUP Packets Received
RO 0x0
5 stsphsercvd

This interrupt is valid only for Control OUT endpoints and only in Scatter Gather DMA mode. This interrupt is generated only after the core has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. The interrupt indicates to the application that the host has switched from data phase to the status phase of a Control Write transfer. The application can use this interrupt to ACK or STALL the Status phase, after it has decoded the data phase. This is applicable only in Case of Scatter Gather DMA mode.

Value Description
0x0 No Status Phase Received for Control Write
0x1 Status Phase Received for Control Write
RO 0x0
4 outtknepdis

Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Value Description
0x0 No OUT Token Received When Endpoint Disabled
0x1 OUT Token Received When Endpoint Disabled
RO 0x0
3 setup

Applies to control OUT endpoints only. Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received SETUP data packet.

Value Description
0x0 No SETUP Phase Done
0x1 SETUP Phase Done
RO 0x0
2 ahberr

Applies to IN and OUT endpoints.This is generated only in Internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

Value Description
0x0 No Interrupt
0x1 AHB Error interrupt
RO 0x0
1 epdisbld

Applies to IN and OUT endpoints. This bit indicates that the endpoint is disabled per the application's request.

Value Description
0x0 No Interrupt
0x1 Endpoint Disabled Interrupt
RO 0x0
0 xfercompl

Applies to IN and OUT endpoints.When Scatter/Gather DMA mode is enabled This field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set. When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Value Description
0x0 No Interrupt
0x1 Transfer Completed Interrupt
RO 0x0