doeptsiz0

The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 1 to 15. When Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00B10`
`usb1`	`0xFFB40000`	`0xFFB40B10`

Offset: 0xB10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`	`supcnt` `RW 0x0`		`Reserved`									`pktcnt` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`xfersize` `RW 0x0`

doeptsiz0 Fields

Bit

Name

Description

Access

Reset

30:29

supcnt

SETUP Packet Count (SUPCnt)This field specifies the number of back-to-back SETUP datapackets the endpoint can receive.

Value	Description
0x1	1 packet
0x2	2 packets
0x3	3 packets

RW

0x0

pktcnt

This field is decremented to zero after a packet is written into the RxFIFO.

RW

0x0

6:0

xfersize

Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be Set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet from the external memory is written to the RxFIFO.

RW

0x0