diepctl0

This register covers Device Control IN Endpoint 0.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00900`
`usb1`	`0xFFB40000`	`0xFFB40900`

Offset: 0x900

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`epena` `RO 0x0`	`epdis` `RO 0x0`	`Reserved`		`snak` `WO 0x0`	`cnak` `WO 0x0`	`txfnum` `RW 0x0`				`stall` `RO 0x0`	`Reserved`	`eptype` `RO 0x0`		`naksts` `RO 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`usbactep` `RO 0x1`	`Reserved`													`mps` `RW 0x0`

diepctl0 Fields

Bit

Name

Description

Access

Reset

epena

When Scatter/Gather DMA mode is enabled, for IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. When Scatter/Gather DMA mode is disabled such as in bufferpointer based DMA mode this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before setting the following interrupts on this endpoint: -Endpoint Disabled -Transfer Completed

Value	Description
0x0	No action
0x1	Endpoint Enabled

RO

0x0

epdis

The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled Interrupt. The application must Set this bit only If Endpoint Enable is already Set for this endpoint.

Value	Description
0x0	No action
0x1	Stop transmitting data on endpoint

RO

0x0

snak

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

Value	Description
0x0	No action
0x1	Set NAK

WO

0x0

cnak

A write to this bit clears the NAK bit for the endpoint.

Value	Description
0x0	No action
0x1	Clear NAK

WO

0x0

25:22

txfnum

for Shared FIFO operation, this value is always Set to 0, indicating that control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO. for Dedicated FIFO operation, this value is Set to the FIFO number that is assigned to IN Endpoint 0.

RW

0x0

stall

The application can only Set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic IN NAK, or Global OUT NAK is Set along with this bit, the STALL bit takes priority.

Value	Description
0x0	No Stall
0x1	Stall Handshake

RO

0x0

19:18

eptype

Hardcoded to 00 for control.

Value	Description
0x0	Endpoint Control 0

RO

0x0

naksts

When this bit is Set, either by the application or core, the core stops transmitting data, even If there is data available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Value	Description
0x0	The core is transmitting non-NAK handshakes based on the FIFO status
0x1	The core is transmitting NAK handshakes on this endpoint

RO

0x0

usbactep

This bit is always SET to 1, indicating that control endpoint 0 is always active in all configurations and interfaces.

Value	Description
0x1	Control endpoint is always active

RO

0x1

1:0

mps

Applies to IN and OUT endpoints.The application must program this field with the maximum packet size for the current logical endpoint.

Value	Description
0x0	64 bytes
0x1	32 bytes
0x2	16 bytes
0x3	8 bytes

RW

0x0