dthrctl

Thresholding is not supported in Slave mode and so this register must not be programmed in Slave mode. for threshold support, the AHB must be run at 60 MHz or higher.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00830`
`usb1`	`0xFFB40000`	`0xFFB40830`

Offset: 0x830

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`				`arbprken` `RW 0x1`	`Reserved`	`rxthrlen` `RW 0x8`									`rxthren` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`ahbthrratio` `RW 0x0`		`txthrlen` `RW 0x8`									`isothren` `RW 0x0`	`nonisothren` `RW 0x0`

dthrctl Fields

Bit

Name

Description

Access

Reset

arbprken

This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is Set to one, Then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By Default the parking is enabled.

Value	Description
0x0	Disable DMA arbiter parking
0x1	Enable DMA arbiter parking for IN endpoints

RW

0x1

25:17

rxthrlen

This field specifies Receive thresholding size in DWORDS.This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight DWORDS. The recommended value for ThrLen is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).

RW

0x8

rxthren

When this bit is Set, the core enables thresholding in the receive direction.

Value	Description
0x0	Disable thresholding
0x1	Enable thresholding in the receive direction

RW

0x0

12:11

ahbthrratio

These bits define the ratio between the AHB threshold and the MAC threshold for the transmit path only. The AHB threshold always remains less than or equal to the USB threshold, because this does not increase overhead. Both the AHB and the MAC threshold must be DWORD-aligned. The application needs to program TxThrLen and the AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold value is not DWORD aligned, the core might not behave correctly. When programming the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB threshold value does not go below 8 DWORDS to meet the USB turnaround time requirements.

Value	Description
0x0	AHB threshold = MAC threshold
0x1	AHB threshold = MAC threshold /2
0x2	AHB threshold = MAC threshold /4
0x3	AHB threshold = MAC threshold /

RW

0x0

10:2

txthrlen

This field specifies Transmit thresholding size in DWORDS. This also forms the MAC threshold and specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmit on the USB. The threshold length has to be at least eight DWORDS when the value of AHBThrRatio is 0. In case the AHBThrRatio is non zero the application needs to ensure that the AHB Threshold value does not go below the recommended eight DWORD. This field controls both isochronous and non-isochronous IN endpoint thresholds. The recommended value for ThrLen is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).

RW

0x8

isothren

When this bit is Set, the core enables thresholding for isochronous IN endpoints.

Value	Description
0x0	No thresholding
0x1	Enables thresholding

RW

0x0

nonisothren

When this bit is Set, the core enables thresholding for Non Isochronous IN endpoints.

Value	Description
0x0	No thresholding
0x1	Enable thresholding

RW

0x0