dvbuspulse

This register specifies the VBUS pulsing time during SRP.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB0082C`
`usb1`	`0xFFB40000`	`0xFFB4082C`

Offset: 0x82C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`				`dvbuspulse` `RW 0x5B8`

dvbuspulse Fields

Bit	Name	Description	Access	Reset
11:0	`dvbuspulse`	Specifies the VBUS pulsing time during SRP. This value equals: VBUS pulsing time in PHY clocks/1,024 The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).	`RW`	`0x5B8`