daint
When a significant event occurs on an
endpoint, a Device All Endpoints Interrupt register interrupts the application using
the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the
Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). There is
one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16
bits for IN endpoints. for a bidirectional endpoint, the corresponding IN and OUT
interrupt bits are used. Bits in this register are set and cleared when the
application sets and clears bits in the corresponding Device Endpoint-n Interrupt
register (DIEPINTn/DOEPINTn).
| Module Instance | Base Address | Register Address |
|---|---|---|
| usb0 | 0xFFB00000 | 0xFFB00818 |
| usb1 | 0xFFB40000 | 0xFFB40818 |
Offset: 0x818
Access: RO
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
outepint15 RO 0x0 |
outepint14 RO 0x0 |
outepint13 RO 0x0 |
outepint12 RO 0x0 |
outepint11 RO 0x0 |
outepint10 RO 0x0 |
outepint9 RO 0x0 |
outepint8 RO 0x0 |
outepint7 RO 0x0 |
outepint6 RO 0x0 |
outepint5 RO 0x0 |
outepint4 RO 0x0 |
outepint3 RO 0x0 |
outepint2 RO 0x0 |
outepint1 RO 0x0 |
outepint0 RO 0x0 |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
inepint15 RO 0x0 |
inepint14 RO 0x0 |
inepint13 RO 0x0 |
inepint12 RO 0x0 |
inepint11 RO 0x0 |
inepint10 RO 0x0 |
inepint9 RO 0x0 |
inepint8 RO 0x0 |
inepint7 RO 0x0 |
inepint6 RO 0x0 |
inepint5 RO 0x0 |
inepint4 RO 0x0 |
inepint3 RO 0x0 |
inepint2 RO 0x0 |
inepint1 RO 0x0 |
inepint0 RO 0x0 |
daint Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 | outepint15 |
|
RO | 0x0 | ||||||
| 30 | outepint14 |
|
RO | 0x0 | ||||||
| 29 | outepint13 |
|
RO | 0x0 | ||||||
| 28 | outepint12 |
|
RO | 0x0 | ||||||
| 27 | outepint11 |
|
RO | 0x0 | ||||||
| 26 | outepint10 |
|
RO | 0x0 | ||||||
| 25 | outepint9 |
|
RO | 0x0 | ||||||
| 24 | outepint8 |
|
RO | 0x0 | ||||||
| 23 | outepint7 |
|
RO | 0x0 | ||||||
| 22 | outepint6 |
|
RO | 0x0 | ||||||
| 21 | outepint5 |
|
RO | 0x0 | ||||||
| 20 | outepint4 |
|
RO | 0x0 | ||||||
| 19 | outepint3 |
|
RO | 0x0 | ||||||
| 18 | outepint2 |
|
RO | 0x0 | ||||||
| 17 | outepint1 |
|
RO | 0x0 | ||||||
| 16 | outepint0 |
|
RO | 0x0 | ||||||
| 15 | inepint15 |
|
RO | 0x0 | ||||||
| 14 | inepint14 |
|
RO | 0x0 | ||||||
| 13 | inepint13 |
|
RO | 0x0 | ||||||
| 12 | inepint12 |
|
RO | 0x0 | ||||||
| 11 | inepint11 |
|
RO | 0x0 | ||||||
| 10 | inepint10 |
|
RO | 0x0 | ||||||
| 9 | inepint9 |
|
RO | 0x0 | ||||||
| 8 | inepint8 |
|
RO | 0x0 | ||||||
| 7 | inepint7 |
|
RO | 0x0 | ||||||
| 6 | inepint6 |
|
RO | 0x0 | ||||||
| 5 | inepint5 |
|
RO | 0x0 | ||||||
| 4 | inepint4 |
|
RO | 0x0 | ||||||
| 3 | inepint3 |
|
RO | 0x0 | ||||||
| 2 | inepint2 |
|
RO | 0x0 | ||||||
| 1 | inepint1 |
|
RO | 0x0 | ||||||
| 0 | inepint0 |
|
RO | 0x0 |