diepmsk

This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00810
usb1 0xFFB40000 0xFFB40810

Offset: 0x810

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

nakmsk

RW 0x0

Reserved

bnainintrmsk

RW 0x0

txfifoundrnmsk

RW 0x0

Reserved

inepnakeffmsk

RW 0x0

intknepmismsk

RW 0x0

intkntxfempmsk

RW 0x0

timeoutmsk

RW 0x0

ahberrmsk

RW 0x0

epdisbldmsk

RW 0x0

xfercomplmsk

RW 0x0

diepmsk Fields

Bit Name Description Access Reset
13 nakmsk

Value Description
0x0 Mask NAK Interrupt
0x1 No Mask NAK Interrupt
RW 0x0
9 bnainintrmsk

Value Description
0x0 Mask BNA Interrupt
0x1 No Mask BNA Interrupt
RW 0x0
8 txfifoundrnmsk

Value Description
0x0 Mask Fifo Underrun Interrupt
0x1 No Mask Fifo Underrun Interrupt
RW 0x0
6 inepnakeffmsk

Value Description
0x0 Mask IN Endpoint NAK Effective Interrupt
0x1 No Mask IN Endpoint NAK Effective Interrupt
RW 0x0
5 intknepmismsk

Value Description
0x0 Mask IN Token received with EP Mismatch Interrupt
0x1 No Mask IN Token received with EP Mismatch Interrupt
RW 0x0
4 intkntxfempmsk

Value Description
0x0 Mask IN Token Received When TxFIFO Empty Interrupt
0x1 No Mask IN Token Received When TxFIFO Empty Interrupt
RW 0x0
3 timeoutmsk

Non-isochronous endpoints

Value Description
0x0 Mask Timeout Condition Interrupt
0x1 No Mask Timeout Condition Interrupt
RW 0x0
2 ahberrmsk

Value Description
0x0 Mask AHB Error Interrupt
0x1 No Mask AHB Error Interrupt
RW 0x0
1 epdisbldmsk

Value Description
0x0 Mask Endpoint Disabled Interrupt
0x1 No Mask Endpoint Disabled Interrupt
RW 0x0
0 xfercomplmsk

Value Description
0x0 Mask Transfer Completed Interrupt
0x1 No Mask Transfer Completed Interrupt
RW 0x0