dsts

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00808`
`usb1`	`0xFFB40000`	`0xFFB40808`

Offset: 0x808

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`										`soffn` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`soffn` `RO 0x0`								`Reserved`				`errticerr` `RO 0x0`	`enumspd` `RO 0x1`		`suspsts` `RO 0x0`

dsts Fields

Bit

Name

Description

Access

Reset

21:8

soffn

When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains a Frame number.

RO

0x0

errticerr

The core sets this bit to report any erratic errors (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at least 2 ms, due to PHY error) seen on the UTMI+ . Due to erratic errors, the otg core goes into Suspended state and an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover.

Value	Description
0x0	No Erratic Error
0x1	Erratic Error

RO

0x0

2:1

enumspd

Indicates the speed at which the otg core has come up after speed detection through a chirp sequence.

Value	Description
0x0	High speed (PHY clock is running at 30 or 60 MHz)
0x1	Full speed (PHY clock is running at 30 or 60 MHz)
0x2	Low speed (PHY clock is running at 6 MHz)
0x3	Full speed (PHY clock is running at 48 MHz)

RO

0x1

suspsts

In Device mode, this bit is Set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when there is no activity on the phy_line_state_i signal for an extended period of time. The core comes out of the suspend: -When there is any activity on the phy_line_state_i signal -When the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig).

Value	Description
0x0	No suspend state
0x1	Suspend state

RO

0x0