hcint14

This register indicates the status of a channel with respect to USB- and AHB-related events. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB006C8`
`usb1`	`0xFFB40000`	`0xFFB406C8`

Offset: 0x6C8

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`desc_lst_rollintr` `RO 0x0`	`xcs_xact_err` `RO 0x0`	`bnaintr` `RO 0x0`	`datatglerr` `RO 0x0`	`frmovrun` `RO 0x0`	`bblerr` `RO 0x0`	`xacterr` `RO 0x0`	`nyet` `RO 0x0`	`ack` `RO 0x0`	`nak` `RO 0x0`	`stall` `RO 0x0`	`ahberr` `RO 0x0`	`chhltd` `RO 0x0`	`xfercompl` `RO 0x0`

hcint14 Fields

Bit

Name

Description

Access

Reset

desc_lst_rollintr

Descriptor rollover interrupt (DESC_LST_ROLLIntr)This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when the corresponding channel's descriptor list rolls over. for non Scatter/Gather DMA mode, this bit is reserved.

Value	Description
0x0	No Descriptor rollover interrupt
0x1	Descriptor rollover interrupt

RO

0x0

xcs_xact_err

This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will not be generated for Isochronous channels.for non Scatter/Gather DMA mode, this bit is reserved.

Value	Description
0x0	No Excessive Transaction Error
0x1	Excessive Transaction Error

RO

0x0

bnaintr

This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the Core to process. BNA will not be generated for Isochronous channels. for non Scatter/Gather DMA mode, this bit is reserved.

Value	Description
0x0	No BNA Interrupt
0x1	BNA Interrupt

RO

0x0

datatglerr

This bit can be set only by the core and the application should write 1 to clear it. In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.

Value	Description
0x0	No Data Toggle Error
0x1	Data Toggle Error

RO

0x0

frmovrun

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No Frame Overrun
0x1	Frame Overrun

RO

0x0

bblerr

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core..This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No Babble Error
0x1	Babble Error

RO

0x0

xacterr

Indicates one of the following errors occurred on the USB.-CRC check failure -Timeout -Bit stuff error -False EOP In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No Transaction Error
0x1	Transaction Error

RO

0x0

nyet

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No NYET Response Received Interrupt
0x1	NYET Response Received Interrupt

RO

0x0

ack

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No ACK Response Received Transmitted Interrupt
0x1	ACK Response Received Transmitted Interrup

RO

0x0

nak

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No NAK Response Received Interrupt
0x1	NAK Response Received Interrupt

RO

0x0

stall

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No Stall Interrupt
0x1	Stall Interrupt

RO

0x0

ahberr

This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

Value	Description
0x0	No AHB error
0x1	AHB error during AHB read/write

RO

0x0

chhltd

In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer. In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following . EOL being set in descriptor . AHB error . Excessive transaction errors . Babble . Stall

Value	Description
0x0	Channel not halted
0x1	Channel Halted

RO

0x0

xfercompl

Transfer completed normally without any errors. This bit can be set only by the core and the application should write 1 to clear it.

Value	Description
0x0	No transfer
0x1	Transfer completed normally without any errors

RO

0x0