hcdma1

This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00534`
`usb1`	`0xFFB40000`	`0xFFB40534`

Offset: 0x534

Access: RW

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`hcdma1` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`hcdma1` `RW 0x0`

hcdma1 Fields

Bit	Name	Description	Access	Reset
31:0	`hcdma1`	Non-Isochronous: This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. This field holds the address of the 2(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as per Table below [31:N] Base Address [N-1:3] Offset [2:0] 000 HS ISOC FS ISOC nTD N nTD N 7 6 1 4 15 7 3 5 31 8 7 6 63 9 15 7 127 10 31 8 255 11 63 9 [N-1:3] (Isoc):[8:3] (Non Isoc): Current Transfer Desc(CTD): Non Isochronous: This value is in terms of number of descriptors. The values can be from 0 to 63. 0 - 1 descriptor. 63 - 64 descriptors. This field indicates the current descriptor processed in the list. This field is updated both by application and the core. for example, if the application enables the channel after programming CTD=5, then the core will start processing the 6th descriptor. The address is obtained by adding a value of (8bytes5=) 40(decimal) to DMAAddr. Isochronous: CTD for isochronous is based on the current frame/microframe value. Need to be set to zero by application.	`RW`	`0x0`