hfir

This register stores the frame interval information for the current speed to which the otg core has enumerated
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00404
usb1 0xFFB40000 0xFFB40404

Offset: 0x404

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

hfirrldctrl

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

frint

RW 0xEA60

hfir Fields

Bit Name Description Access Reset
16 hfirrldctrl

This bit allows dynamic reloading of the HFIR register during run time. 0x0 : The HFIR cannot be reloaded dynamically0x1: the HFIR can be dynamically reloaded during runtime. This bit needs to be programmed during initial configuration and its value should not be changed during runtime.

Value Description
0x0 The HFIR cannot be reloaded dynamically
0x1 The HFIR can be dynamically reloaded during runtime
RW 0x0
15:0 frint

The value that the application programs to this field specifies the interval between two consecutive SOFs (FS) or micro- SOFs (HS) or Keep-Alive tokens (HS). This field contains the number of PHY clocks that constitute the required frame interval. The Default value Set in this field for a FS operation when the PHY clock frequency is 60 MHz. The application can write a value to this register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been Set. If no value is programmed, the core calculates the value based on the PHY clock specified in the FS/LS PHY Clock Select field of the Host Configuration register (HCFG.FSLSPclkSel). Do not change the value of this field after the initial configuration. 125 s * (PHY clock frequency for HS) 1 ms * (PHY clock frequency for FS/LS)

 RW 0xEA60