ghwcfg4

This register contains the configuration options.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00050
usb1 0xFFB40000 0xFFB40050

Offset: 0x50

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

dma

RO 0x1

dma_configuration

RO 0x1

ineps

RO 0xF

dedfifomode

RO 0x1

sessendfltr

RO 0x0

bvalidfltr

RO 0x0

avalidfltr

RO 0x0

vbusvalidfltr

RO 0x0

iddgfltr

RO 0x0

numctleps

RO 0xF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

phydatawidth

RO 0x0

Reserved

hibernation

RO 0x0

ahbfreq

RO 0x1

partialpwrdn

RO 0x0

numdevperioeps

RO 0x0

ghwcfg4 Fields

Bit Name Description Access Reset
31 dma

Enable descriptor based scatter/gather DMA. When enabled, DMA operations will be serviced with descriptor based scatter/gather DMA

Value Description
0x1 Dynamic configuration
RO 0x1
30 dma_configuration

Selects bewteen scatter and nonscatter configuration

Value Description
0x0 Non-Scatter/Gather DMA configuration
0x1 Scatter/Gather DMA configuration
RO 0x1
29:26 ineps

Number of Device Mode IN Endpoints Including Control.

Value Description
0x0 In Endpoint 1
0x1 In Endpoint 2
0x2 In Endpoint 3
0x3 In Endpoint 4
0x4 In Endpoint 5
0x5 In Endpoint 6
0x6 In Endpoint 7
0x7 In Endpoint 8
0x8 In Endpoint 9
0x9 In Endpoint 10
0xa In Endpoint 11
0xb In Endpoint 12
0xc In Endpoint 13
0xd In Endpoint 14
0xe In Endpoint 15
0xf In Endpoint 16
RO 0xF
25 dedfifomode

Specifies whether Dedicated Transmit FIFOs should be enabled in device mode.

Value Description
0x1 Dedicated Transmit FIFO Operation enabled
RO 0x1
24 sessendfltr

Specifies whether to add a filter on the session_end input from the PHY.

Value Description
0x0 No filter
RO 0x0
23 bvalidfltr

Specifies whether to add a filter on the b_valid input from the PHY.

Value Description
0x0 No Filter
RO 0x0
22 avalidfltr

Specifies whether to add a filter on the b_valid input from the PHY.

Value Description
0x0 No filter
RO 0x0
21 vbusvalidfltr

Vbus Valid Filter Enabled (VBusValidFltr) 0: No filter 1: Filter(coreConsultant parameter: OTG_EN_VBUSVALID_FILTER)

Value Description
0x0 Vbus Valid Filter Disabled
RO 0x0
20 iddgfltr

Specifies whether to add a filter on the iddig input from the PHY. This is not relevant since we only support ULPI and there is no iddig pin exposed to I/O pads.

Value Description
0x0 Iddig Filter Disabled
RO 0x0
19:16 numctleps

Specifies the number of Device mode control endpoints in addition to control endpoint 0, which is always present. Range: 0-15.

Value Description
0x0 End point 0
0x1 End point 1
0x2 End point 2
0x3 End point 3
0x4 End point 4
0x5 End point 5
0x6 End point 6
0x7 End point 7
0x8 End point 8
0x9 End point 9
0xa End point 10
0xb End point 11
0xc End point 12
0xd End point 13
0xe End point 14
0xf End point 15
RO 0xF
15:14 phydatawidth

Uses a ULPI interface only. Hence only 8-bit setting is relevant. This setting should not matter since UTMI is not enabled.

 RO 0x0
6 hibernation

Enables power saving mode hibernation.

Value Description
0x0 Hibernation feature disabled
RO 0x0
5 ahbfreq

When the AHB frequency is less than 60 MHz, 4-deep clock-domain crossing sink and source buffers are instantiated between the MAC and the Packet FIFO Controller (PFC); otherwise, two-deep buffers are sufficient.

Value Description
0x1 Minimum AHB Frequency Less Than 60 MH
RO 0x1
4 partialpwrdn

Specifies whether to enable power optimization.

Value Description
0x0 Partial Power Down disabled
RO 0x0
3:0 numdevperioeps

The maximum number of device IN operations is 16 active at any time including endpoint 0, which is always present. This parameter determines the number of device mode Tx FIFOs to be instantiated.

 RO 0x0