gusbcfg

This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB0000C`
`usb1`	`0xFFB40000`	`0xFFB4000C`

Offset: 0xC

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`corrupttxpkt` `WO 0x0`	`forcedevmode` `RW 0x0`	`forcehstmode` `RW 0x0`	`txenddelay` `RW 0x0`	`Reserved`		`ulpi` `RW 0x0`	`indicator` `RW 0x0`	`complement` `RW 0x0`	`termseldlpulse` `RW 0x0`	`ulpiextvbusindicator` `RW 0x0`	`ulpiextvbusdrv` `RW 0x0`	`ulpiclksusm` `RW 0x0`	`ulpiautores` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`usbtrdtim` `RW 0x5`				`hnpcap` `RW 0x0`	`srpcap` `RW 0x0`	`ddrsel` `RW 0x0`	`physel` `RO 0x0`	`fsintf` `RO 0x0`	`ulpi_utmi_sel` `RO 0x1`	`phyif` `RO 0x0`	`toutcal` `RW 0x0`

gusbcfg Fields

Bit

Name

Description

Access

Reset

corrupttxpkt

Mode: Host and device. This bit is for debug purposes only. Never Set this bit to 1. The application should always write 0 to this bit.

Value	Description
0x0	Normal Mode
0x1	Debug Mode

WO

0x0

forcedevmode

Mode:Host and device. Writing a 1 to this bit forces the core to device mode. After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro-sec is sufficient.

Value	Description
0x0	Normal Mode
0x1	Force Device Mode

RW

0x0

forcehstmode

Mode:Host and device. Writing a 1 to this bit forces the core to host mode After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro-sec is sufficient.

Value	Description
0x0	Normal Mode
0x1	Force Host Mode

RW

0x0

txenddelay

Mode: Device only. Set to non UTMI+.

Value	Description
0x0	Normal Mode

RW

0x0

ulpi

Mode:Host only. Controls circuitry built into the PHY for protecting the ULPI interface when the link tri-states STP and data. Any pull-ups or pull-downs employed by this feature can be disabled.

Value	Description
0x0	Enables the interface protect circuit
0x1	Disables the interface protect circuit

RW

0x0

indicator

Mode:Host only. Controls wether the Complement Output is qualified with the Internal Vbus Valid comparator before being used in the Vbus State in the RX CMD.

Value	Description
0x0	Complement Output signal is qualified with the Internal VbusValid comparator
0x1	Complement Output signal is not qualified with the Internal VbusValid comparator

RW

0x0

complement

Mode:Host only. Controls the PHY to invert the ExternalVbusIndicator inputsignal, generating the ComplementOutput. Please refer to the ULPI Spec for more detail.

Value	Description
0x0	PHY does not invert ExternalVbusIndicator signal
0x1	PHY does invert ExternalVbusIndicator signal

RW

0x0

termseldlpulse

Mode:Device only. This bit selects utmi_termselect to drive data line pulse during SRP.

Value	Description
0x0	Data line pulsing using utmi_txvalid
0x1	Data line pulsing using utmi_termsel

RW

0x0

ulpiextvbusindicator

Mode:Host only. This bit indicates to the ULPI PHY to use an external VBUS overcurrent indicator.

Value	Description
0x0	PHY uses internal VBUS valid comparator
0x1	PHY uses external VBUS valid comparator

RW

0x0

ulpiextvbusdrv

Mode:Host only. This bit selects between internal or external supply to drive 5V on VBUS, in ULPI PHY.

Value	Description
0x0	PHY drives VBUS using internal charge pump
0x1	PHY drives VBUS using external supply

RW

0x0

ulpiclksusm

Mode:Host and Device. This bit sets the ClockSuspendM bit in the Interface Control register on the ULPI PHY. This bit applies only in serial or carkit modes.

Value	Description
0x0	PHY powers down internal clock during suspend
0x1	PHY does not power down internal clock

RW

0x0

ulpiautores

Mode:Host and Device. This bit sets the AutoResume bit in the Interface Control register on the ULPI PHY.

Value	Description
0x0	PHY does not use AutoResume feature
0x1	PHY uses AutoResume feature

RW

0x0

13:10

usbtrdtim

Mode: Device only. Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The value is calculated for the minimum AHB frequency of 30 MHz. USB turnaround time is critical for certification where long cables and 5-Hubs are used, so If you need the AHB to run at less than 30 MHz, and If USB turnaround time is not critical, these bits can be programmed to a larger value.

Value	Description
0x9	MAC interface is 8-bit UTMI+.

RW

0x5

hnpcap

Mode:Host and Device. The application uses this bit to control the otg core's HNP capabilities.

Value	Description
0x0	HNP capability is not enabled.
0x1	HNP capability is enabled

RW

0x0

srpcap

Mode:Host and Device. The application uses this bit to control the otg core SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate VBUS and start a session. This bit is writable only If an SRP mode was specified for Mode of Operation in coreConsultant (parameter OTG_MODE). Otherwise, reads Return 0.

Value	Description
0x0	SRP capability is not enabled
0x1	SRP capability is enabled

RW

0x0

ddrsel

Mode:Host and Device. The application uses this bit to select a Single Data Rate (SDR) ULPI interface. DDR is not supported.

Value	Description
0x0	Single Data Rate ULPI Interfacewith 8-bit-wide data bus
0x1	Reserved

RW

0x0

physel

Mode:Host and Device. The application uses USB 2.0.

Value	Description
0x0	USB 2.0 high-speed ULPI

RO

0x0

fsintf

Mode:Host and Device. The application can Set this bit to select between the 3- and 6-pin interfaces, and access is Read and Write.

Value	Description
0x0	6-pin unidirectional full-speed serial interface
0x1	3-pin bidirectional full-speed serial interface

RO

0x0

ulpi_utmi_sel

Mode:Host and Device. The application uses ULPI Only in 8bit mode.

Value	Description
0x0	ULPI PHY
0x1	UTMI PHY

RO

0x1

phyif

Mode:Host and Device. This application uses a ULPI interface only. Hence only 8-bit setting is relevant. This setting should not matter since UTMI is not enabled.

Value	Description
0x0	PHY 8bit Mode

RO

0x0

2:0

toutcal

Mode:Host and Device. The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are: High-speed operation: -One 30-MHz PHY clock = 16 bit times -One 60-MHz PHY clock = 8 bit times Full-speed operation: -One 30-MHz PHY clock = 0.4 bit times -One 60-MHz PHY clock = 0.2 bit times -One 48-MHz PHY clock = 0.25 bit times

RW

0x0