AHB_or_AXI_Status

This register provides the active status of the AXI interface's read and write channels. This register is useful for debugging purposes.

Module Instance	Base Address	Register Address
`emac0`	`0xFF700000`	`0xFF70102C`
`emac1`	`0xFF702000`	`0xFF70302C`

Offset: 0x102C

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`axirdsts` `RO 0x0`	`axwhsts` `RO 0x0`

AHB_or_AXI_Status Fields

Bit	Name	Description	Access	Reset
1	`axirdsts`	When high, it indicates that AXI Master's read channel is active and transferring data.	`RO`	`0x0`
0	`axwhsts`	When high, it indicates that AXI Master's write channel is active and transferring data	`RO`	`0x0`