AXI_Bus_Mode

The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly used to control the burst splitting and the number of outstanding requests.

Module Instance	Base Address	Register Address
`emac0`	`0xFF700000`	`0xFF701028`
`emac1`	`0xFF702000`	`0xFF703028`

Offset: 0x1028

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`en_lpi` `RW 0x0`	`lpi_xit_frm` `RW 0x0`	`Reserved`						`wr_osr_lmt` `RW 0x1`				`rd_osr_lmt` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`onekbbe` `RW 0x0`	`axi_aal` `RO 0x0`	`Reserved`								`blen16` `RW 0x0`	`blen8` `RW 0x0`	`blen4` `RW 0x0`	`undefined` `RO 0x1`

AXI_Bus_Mode Fields

Bit

Name

Description

Access

Reset

en_lpi

When set to 1, this bit enables the LPI mode supported by the AXI master and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller.

Value	Description
0x0	Disable LPI Mode
0x1	Enable LPI Mode

RW

0x0

lpi_xit_frm

When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the Remote Wake Up Packet is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. This bit must be set to 0.

Value	Description
0x0	Do Not exit LPI Mode with Magic Packet
0x1	Exit LPI Mode with Magic Packet

RW

0x0

23:20

wr_osr_lmt

AXI Maximum Write OutStanding Request Limit

RW

0x1

19:16

rd_osr_lmt

This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1

RW

0x1

onekbbe

1 KB Boundary Crossing Enable for the GMAC-AXI Master When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI Master performs burst transfers that do not cross 4 KB boundary.

Value	Description
0x0	4K boundary
0x1	1K boundary

RW

0x0

axi_aal

This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels.

Value	Description
0x0	No Address-Alignment Bursts
0x1	Address-Alignmnet Bursts

RO

0x0

blen16

When this bit is set to 1 or UNDEFINED is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI Master interface.

Value	Description
0x0	AXI No Fixed Busrts
0x1	AXI Fixed Burst BLEN = 16

RW

0x0

blen8

When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI Master interface. Setting this bit has no effect when UNDEFINED is set to 1.

Value	Description
0x0	AXI No Fixed Busrts
0x1	AXI Fixed Burst BLEN = 8

RW

0x0

blen4

When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI Master interface. Setting this bit has no effect when UNDEFINED is set to 1.

Value	Description
0x0	AXI No Fixed Busrts
0x1	AXI Fixed Burst BLEN = 4

RW

0x0

undefined

This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register[16]). * When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:1]. * When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN16, BLEN8, or BLEN4, or a burst length of 1.

Value	Description
0x0	Fixed Burst Lengths 4 to 16
0x1	Any Burst Length up to max

RO

0x1