Missed_Frame_And_Buffer_Overflow_Counter

The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate missed frames because of the host buffer being unavailable. Bits[27:17] indicate missed frames because of buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL.

Module Instance	Base Address	Register Address
`emac0`	`0xFF700000`	`0xFF701020`
`emac1`	`0xFF702000`	`0xFF703020`

Offset: 0x1020

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`ovfcntovf` `RO 0x0`	`ovffrmcnt` `RO 0x0`											`miscntovf` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`misfrmcnt` `RO 0x0`

Missed_Frame_And_Buffer_Overflow_Counter Fields

Bit	Name	Description	Access	Reset
28	`ovfcntovf`	Overflow bit for FIFO Overflow Counter	`RO`	`0x0`
27:17	`ovffrmcnt`	This field indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal mtl_rxoverflow_o. The counter is cleared when this register is read with mci_be_i[2] at 1'b1.	`RO`	`0x0`
16	`miscntovf`	Overflow bit for Missed Frame Counter	`RO`	`0x0`
15:0	`misfrmcnt`	This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1'b1.	`RO`	`0x0`