Hash_Table_Reg0

This register contains the first 32 bits of the hash table. The 256-bit Hash table is used for group address filtering. For hash filtering, the content of the destination address in the incoming frame is passed through the CRC logic and the upper eight bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register. For example, a hash value of 8b'10111111 selects Bit 31 of the Hash Table Register 5. The hash value of the destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1'b1, the frame is accepted. Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the multicast hash values. Because the Hash Table register is double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written. Note: Because of double-synchronization, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.

Module Instance	Base Address	Register Address
`emac0`	`0xFF700000`	`0xFF700500`
`emac1`	`0xFF702000`	`0xFF702500`

Offset: 0x500

Access: RW

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ht31t0` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ht31t0` `RW 0x0`

Hash_Table_Reg0 Fields

Bit	Name	Description	Access	Reset
31:0	`ht31t0`	This field contains the first 32 Bits (31:0) of the Hash table.	`RW`	`0x0`