Interrupt_Status

The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt events are generated only when the corresponding optional feature is enabled.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700038
emac1 0xFF702000 0xFF702038

Offset: 0x38

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

lpiis

RO 0x0

tsis

RO 0x0

Reserved

mmcrxipis

RO 0x0

mmctxis

RO 0x0

mmcrxis

RO 0x0

mmcis

RO 0x0

Reserved

pcsancis

RO 0x0

pcslchgis

RO 0x0

rgsmiiis

RO 0x0

Interrupt_Status Fields

Bit Name Description Access Reset
10 lpiis

This bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved.

Value Description
0x0 LPI Interrupt Status Disabled
0x1 LPI Interrupt Status Enabled
RO 0x0
9 tsis

This bit is set when any of the following conditions is true: * The system time value equals or exceeds the value specified in the Target Time High and Low registers. * There is an overflow in the seconds register. * The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status Register). When set, this bit indicates that the system time value is equal to or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this bit. In all other modes, this bit is reserved.

Value Description
0x0 Timestamp Interrupt Status Disabled
0x1 Timestamp Interrupt Status Enabled
RO 0x0
7 mmcrxipis

This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

Value Description
0x0 MMC Receive Checksum Offload Interrupt Status Disabled
0x1 MMC Receive Checksum Offload Interrupt Status Enabled
RO 0x0
6 mmctxis

This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

Value Description
0x0 MMC Transmit Interrupt Status Disabled
0x1 MMC Transmit Interrupt Status Enabled
RO 0x0
5 mmcrxis

This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

Value Description
0x0 MMC Receive Interrupt Status Disabled
0x1 MMC Receive Interrupt Status Enabled
RO 0x0
4 mmcis

This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low.

Value Description
0x0 MMC Interrupt Status Disabled
0x1 MMC Interrupt Status Enabled
RO 0x0
2 pcsancis

This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. NOTE: You can ignore this bit if you are not using TBI, RTBI or SGMII PHY interface.

 RO 0x0
1 pcslchgis

This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. NOTE: You can ignore this bit if you are not using TBI, RTBI or SGMII PHY interface

 RO 0x0
0 rgsmiiis

This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status Register.

Value Description
0x0 Link No Change
0x1 Link Change
RO 0x0