flashcmdaddr
| Module Instance | Base Address | Register Address |
|---|---|---|
| qspiregs | 0xFF705000 | 0xFF705094 |
Offset: 0x94
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
addr RW 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
addr RW 0x0 |
|||||||||||||||
flashcmdaddr Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:0 | addr | This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control register. |
RW | 0x0 |