irqstat

The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when legacy SPI mode is active.
Module Instance Base Address Register Address
qspiregs 0xFF705000 0xFF705040

Offset: 0x40

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

indsramfull

RW 0x0

rxfull

RW 0x0

rxthreshcmp

RW 0x0

txfull

RW 0x0

txthreshcmp

RW 0x1

rxover

RW 0x0

indxfrlvl

RW 0x0

illegalacc

RW 0x0

protwrattempt

RW 0x0

indrdreject

RW 0x0

indopdone

RW 0x0

underflowdet

RW 0x0

Reserved

irqstat Fields

Bit Name Description Access Reset
12 indsramfull

Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation

Value Description
0x1 SRAM is full
0x0 SRAM is not full
RW 0x0
11 rxfull

Indicates that the receive FIFO is full or not. Only relevant in SPI legacy mode.

Value Description
0x0 Receive FIFO Not Full
0x1 Receive FIFO Full
RW 0x0
10 rxthreshcmp

Indicates the number of entries in the receive FIFO with respect to the threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode.

Value Description
0x0 FIFO has <= RXTHRESH entries
0x1 FIFO has > RXTHRESH entries
RW 0x0
9 txfull

Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy mode.

Value Description
0x0 Transmit FIFO Not Full
0x1 Transmit FIFO Full
RW 0x0
8 txthreshcmp

Indicates the number of entries in the transmit FIFO with respect to the threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode.

Value Description
0x0 FIFO has > TXTHRESH entries
0x1 FIFO has <= TXTHRESH entries
RW 0x1
7 rxover

This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0 : no overflow has been detected. 1 : an overflow has occurred.

Value Description
0x1 Receive Overflow
0x0 No Receive Overflow
RW 0x0
6 indxfrlvl

Indirect Transfer Watermark Level Reached

Value Description
0x1 Water level reached
0x0 No water level reached
RW 0x0
5 illegalacc

Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger.

Value Description
0x1 Illegal AHB attempt
0x0 No Illegal AHB attempt
RW 0x0
4 protwrattempt

Write to protected area was attempted and rejected.

Value Description
0x1 Write Attempt to protected area
0x0 No Write Attempt
RW 0x0
3 indrdreject

Indirect operation was requested but could not be accepted. Two indirect operations already in storage.

Value Description
0x1 Indirect Operation Requested
0x0 No Indirect Operation
RW 0x0
2 indopdone

Controller has completed last triggered indirect operation

Value Description
0x1 Completed Indirect Operation
0x0 No Indirect Operation
RW 0x0
1 underflowdet

An underflow is detected when an attempt to transfer data is made when the transmit FIFO is empty. This may occur when the AHB write data is being supplied too slowly to keep up with the requested write operation. This bit is reset only by a system reset and cleared only when the register is read.

Value Description
0x1 Underflow
0x0 No Underflow
RW 0x0