devwr

Module Instance	Base Address	Register Address
`qspiregs`	`0xFF705000`	`0xFF705008`

Offset: 0x8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`dummywrclks` `RW 0x0`					`Reserved`						`datawidth` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`addrwidth` `RW 0x0`		`Reserved`				`wropcode` `RW 0x2`

devwr Fields

Bit

Name

Description

Access

Reset

28:24

dummywrclks

Number of dummy clock cycles required by device for write instruction.

RW

0x0

17:16

datawidth

Sets write data transfer width (1, 2, or 4 bits).

Value	Description
0x0	Write data transferred on DQ0. Supported by all SPI flash devices
0x1	Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
0x2	Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

RW

0x0

13:12

addrwidth

Sets write address transfer width (1, 2, or 4 bits).

Value	Description
0x0	Write address transferred on DQ0. Supported by all SPI flash devices
0x1	Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
0x2	Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

RW

0x0

7:0

wropcode

Write Opcode

RW

0x2