mintsts

Describes state of Masked Interrupt Register.
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF704040

Offset: 0x40

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

sdio_interrupt

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ebe

RO 0x0

acd

RO 0x0

strerr

RO 0x0

hlwerr

RO 0x0

fifoovunerr

RO 0x0

dshto

RO 0x0

datardto

RO 0x0

respto

RO 0x0

datacrcerr

RO 0x0

respcrcerr

RO 0x0

rxfifodr

RO 0x0

dttxfifodr

RO 0x0

dt

RO 0x0

cmd_done

RO 0x0

resp

RO 0x0

cd

RO 0x0

mintsts Fields

Bit Name Description Access Reset
16 sdio_interrupt

Interrupt from SDIO card: one bit for each card. Bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt). In MMC-Ver3.3-only mode, bits always 0.

Value Description
0x1 SDIO interrupt from card
0x0 No SDIO interrupt from card
RO 0x0
15 ebe

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 End-bit error Mask
0x1 End-bit error No Mask
RO 0x0
14 acd

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Auto command done Mask
0x1 Auto command done No Mask
RO 0x0
13 strerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Start-bit error Mask
0x1 Start-bit error No Mask
RO 0x0
12 hlwerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Hardware locked write error Mask
0x1 Hardware locked write error No Mask
RO 0x0
11 fifoovunerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 FIFO underrun/overrun error Mask
0x1 FIFO underrun/overrun error No Mask
RO 0x0
10 dshto

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Data starvation by host timeout Mask
0x1 Data starvation by host timeout No Mask
RO 0x0
9 datardto

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Data read timeout Mask
0x1 Data read timeout No Mask
RO 0x0
8 respto

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Response timeout Mask
0x1 Response timeout No Mask
RO 0x0
7 datacrcerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Data CRC error Mask
0x1 Data CRC error No Mask
RO 0x0
6 respcrcerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Response CRC error Mask
0x1 Response CRC error No Mask
RO 0x0
5 rxfifodr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Receive FIFO data request Mask
0x1 Receive FIFO data request No Mask
RO 0x0
4 dttxfifodr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Transmit FIFO data request Mask
0x1 Transmit FIFO data request No Mask
RO 0x0
3 dt

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Data transfer over Mask
0x1 Data transfer over No Mask
RO 0x0
2 cmd_done

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Command Done Mask
0x1 Command Done No Mask
RO 0x0
1 resp

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Response error Mask
0x1 Response error No Mask
RO 0x0
0 cd

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Value Description
0x0 Card Detected Mask
0x1 Card Detected No Mask
RO 0x0