clkdiv
Divides Clock sdmmc_clk.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sdmmc | 0xFF704000 | 0xFF704008 |
Offset: 0x8
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
clk_divider0 RW 0x0 |
||||||||||||||
clkdiv Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 7:0 | clk_divider0 | Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on. |
RW | 0x0 |