DMA registers Register Descriptions Offset: 0x700 dma_enable dma_intr DMA interrupt register dma_intr_en Enables corresponding interrupt bit in dma interrupt register target_err_addr_lo Transaction address for which controller initiator interface received an ERROR target response. target_err_addr_hi Transaction address for which controller initiator interface received an ERROR target response. flash_burst_length chip_interleave_enable_and_allow_int_reads no_of_blocks_per_lun lun_status_cmd Indicates the command to be sent while checking status of the next LUN.