features

Shows Available hardware features or attributes

Module Instance	Base Address	Register Address
`nandregs`	`0xFFB80000`	`0xFFB803F0`

Offset: 0x3F0

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`lba` `RO 0x0`	`dfi_intf` `RO 0x0`	`index_addr` `RO 0x1`	`gpreg` `RO 0x0`	`xdma_sideband` `RO 0x0`	`partition` `RO 0x0`	`cmd_dma` `RO 0x0`	`dma` `RO 0x1`	`Reserved`				`n_banks` `RO 0x1`

features Fields

Bit	Name	Description	Access	Reset
13	`lba`	if set, hardware supports Toshiba LBA devices.	`RO`	`0x0`
12	`dfi_intf`	if set, hardware supports ONFI2.x synchronous interface.	`RO`	`0x0`
11	`index_addr`	if set, hardware support only Indexed addressing.	`RO`	`0x1`
10	`gpreg`	if set, General purpose registers are is present in hardware.	`RO`	`0x0`
9	`xdma_sideband`	if set, Side band DMA signals are present in hardware.	`RO`	`0x0`
8	`partition`	if set, Partition logic is present in hardware.	`RO`	`0x0`
7	`cmd_dma`	Not implemented.	`RO`	`0x0`
6	`dma`	if set, DATA-DMA is present in hardware.	`RO`	`0x1`
1:0	`n_banks`	Maximum number of banks supported by hardware. This is an encoded value. [list][]0 - Two banks []1 - Four banks []2 - Eight banks []3 - Sixteen banks[/list]	`RO`	`0x1`