cs_setup_cnt

Chip select setup time

Module Instance	Base Address	Register Address
`nandregs`	`0xFFB80000`	`0xFFB80220`

Offset: 0x220

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`											`value` `RW 0x3`

cs_setup_cnt Fields

Bit	Name	Description	Access	Reset
4:0	`value`	Number of nand_mp_clk cycles required for meeting chip select setup time. This register refers to device timing parameter Tcs. The value in this registers reflects the extra setup cycles for chip select before read/write enable signal is set low. The default value is calculated for ONFI Timing mode 0 Tcs = 70ns and maximum nand_mp_clk period of 4ns for 1x/4x clock multiple for 16ns cycle time device.	`RW`	`0x3`