max_rd_delay
Max round trip read data delay for data capture
| Module Instance | Base Address | Register Address |
|---|---|---|
| nandregs | 0xFFB80000 | 0xFFB80210 |
Offset: 0x210
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
value RW 0x0 |
||||||||||||||
max_rd_delay Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 3:0 | value | Number of nand_mp_clk cycles after generation of feedback nand_mp_clk pulse when it is safe to synchronize received data to nand_mp_clk domain. Data should have been registered with nand_mp_clk and stable by the time max_rd_delay cycles has elapsed. A default value of zero will mean a value of nand_mp_clk multiple minus one. |
RW | 0x0 |