two_row_addr_cycles

Attached device has only 2 ROW address cycles

Module Instance	Base Address	Register Address
`nandregs`	`0xFFB80000`	`0xFFB80190`

Offset: 0x190

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`flag` `RW 0x0`

two_row_addr_cycles Fields

Bit	Name	Description	Access	Reset
0	`flag`	This flag must be set for devices which allow for 2 ROW address cycles instead of the usual 3. Alternatively, the TWOROWADDR field of the System Manager NANDGRP_BOOTSTRAP register when asserted will set this flag.	`RW`	`0x0`