re_2_we
Timing parameter between re high to we low (Trhw)
| Module Instance | Base Address | Register Address |
|---|---|---|
| nandregs | 0xFFB80000 | 0xFFB80120 |
Offset: 0x120
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
value RW 0x32 |
||||||||||||||
re_2_we Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 5:0 | value | Signifies the number of bus interface nand_mp_clk clocks that should be introduced between read enable going high to write enable going low. The number of clocks is the function of device parameter Trhw and controller clock frequency. |
RW | 0x32 |