global_int_enable

Global Interrupt enable and Error/Timeout disable.

Module Instance	Base Address	Register Address
`nandregs`	`0xFFB80000`	`0xFFB800F0`

Offset: 0xF0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`error_rpt_disable` `RW 0x0`	`Reserved`			`timeout_disable` `RW 0x0`	`Reserved`			`flag` `RW 0x0`

global_int_enable Fields

Bit	Name	Description	Access	Reset
8	`error_rpt_disable`	Command and ECC uncorrectable failures will not be reported when this bit is set	`RW`	`0x0`
4	`timeout_disable`	Watchdog timer logic will be de-activated when this bit is set.	`RW`	`0x0`
0	`flag`	Host will receive an interrupt only when this bit is set.	`RW`	`0x0`