erase_wait_cnt
Wait count value for Erase operation
| Module Instance | Base Address | Register Address |
|---|---|---|
| nandregs | 0xFFB80000 | 0xFFB80040 |
Offset: 0x40
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
value RW 0x1F4 |
|||||||||||||||
erase_wait_cnt Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:0 | value | Number of clock cycles after issue of erase operation before NAND Flash Controller polls for status. This values is of relevance for status polling mode of operation and has been provided to minimize redundant polling after issuing a command. After a erase command, the first polling will happen after this many number of cycles have elapsed and then on polling will happen every int_mon_cyccnt cycles. The default values is equal to the default value of int_mon_cyccnt. The controller internally multiplies the value programmed into this register by 16 to provide a wider range for polling. |
RW | 0x1F4 |