Master Register Group Register Descriptions Registers associated with master interfaces in the L3 Interconnect. Note that a master in the L3 Interconnect connects to a slave in a module. Offset: 0x2000 L4 MAIN Register Descriptions Registers associated with the L4 MAIN master. This master is used to access the APB slaves on the L4 MAIN bus. L4 SP Register Descriptions Registers associated with the L4 SP master. This master is used to access the APB slaves on the L4 SP bus. L4 MP Register Descriptions Registers associated with the L4 MP master. This master is used to access the APB slaves on the L4 MP bus. L4 OSC1 Register Descriptions Registers associated with the L4 OSC1 master. This master is used to access the APB slaves on the L4 OSC1 bus. L4 SPIM Register Descriptions Registers associated with the L4 SPIM master. This master is used to access the APB slaves on the L4 SPIM bus. STM Register Descriptions Registers associated with the STM master. This master is used to access the STM AXI slave. LWHPS2FPGA Register Descriptions Registers associated with the LWHPS2FPGA AXI Bridge master. This master is used to access the LWHPS2FPGA AXI Bridge slave. This slave is used to access the registers for all 3 AXI bridges and to access slaves in the FPGA connected to the LWHPS2FPGA AXI Bridge. USB1 Register Descriptions Registers associated with the USB1 master. This master is used to access the registers in USB1. NANDDATA Register Descriptions Registers associated with the NANDDATA master. This master is used to access data in the NAND flash controller. USB0 Register Descriptions Registers associated with the USB0 master. This master is used to access the registers in USB0. NANDREGS Register Descriptions Registers associated with the NANDREGS master. This master is used to access the registers in the NAND flash controller. QSPIDATA Register Descriptions Registers associated with the QSPIDATA master. This master is used to access data in the QSPI flash controller. FPGAMGRDATA Register Descriptions Registers associated with the FPGAMGRDATA master. This master is used to send FPGA configuration image data to the FPGA Manager. HPS2FPGA Register Descriptions Registers associated with the HPS2FPGA AXI Bridge master. This master is used to access the HPS2FPGA AXI Bridge slave. This slave is used to access slaves in the FPGA connected to the HPS2FPGA AXI Bridge. ACP Register Descriptions Registers associated with the ACP master. This master is used to access the MPU ACP slave via the ACP ID Mapper. Boot ROM Register Descriptions Registers associated with the Boot ROM master. This master is used to access the contents of the Boot ROM. On-chip RAM Register Descriptions Registers associated with the On-chip RAM master. This master is used to access the contents of the On-chip RAM.