wr_tidemark
Controls the release of the transaction in the write data FIFO.
| Module Instance | Base Address | Register Address |
|---|---|---|
| l3regs | 0xFF800000 | 0xFF824040 |
Offset: 0x24040
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
level RW 0x4 |
||||||||||||||
wr_tidemark Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 3:0 | level | Stalls the transaction in the write data FIFO until the number of occupied slots in the write data FIFO exceeds the level. Note that the transaction is released before this level is achieved if the network receives the WLAST beat or the write FIFO becomes full. |
RW | 0x4 |