l4sp

Controls security settings for L4 SP peripherals.
Module Instance Base Address Register Address
l3regs 0xFF800000 0xFF80000C

Offset: 0xC

Access: WO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sptimer1

WO 0x0

can1

WO 0x0

can0

WO 0x0

uart1

WO 0x0

uart0

WO 0x0

i2c3

WO 0x0

i2c2

WO 0x0

i2c1

WO 0x0

i2c0

WO 0x0

sptimer0

WO 0x0

sdrregs

WO 0x0

l4sp Fields

Bit Name Description Access Reset
10 sptimer1

Controls whether secure or non-secure masters can access the SP Timer 1 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
9 can1

Controls whether secure or non-secure masters can access the CAN 1 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
8 can0

Controls whether secure or non-secure masters can access the CAN 0 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
7 uart1

Controls whether secure or non-secure masters can access the UART 1 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
6 uart0

Controls whether secure or non-secure masters can access the UART 0 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
5 i2c3

Controls whether secure or non-secure masters can access the I2C3 (EMAC 1) slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
4 i2c2

Controls whether secure or non-secure masters can access the I2C2 (EMAC 0) slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
3 i2c1

Controls whether secure or non-secure masters can access the I2C1 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
2 i2c0

Controls whether secure or non-secure masters can access the I2C0 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
1 sptimer0

Controls whether secure or non-secure masters can access the SP Timer 0 slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0
0 sdrregs

Controls whether secure or non-secure masters can access the SDRAM Registers slave.

Value Description
0x0 The slave can only be accessed by a secure master.
0x1 The slave can only be accessed by a secure or non-secure masters.
WO 0x0