remap

The L3 interconnect has separate address maps for the various L3 Masters. Generally, the addresses are the same for most masters. However, the sparse interconnect of the L3 switch causes some masters to have holes in their memory maps. The remap bits are not mutually exclusive. Each bit can be set independently and in combinations. Priority for the bits is determined by the bit offset: lower offset bits take precedence over higher offset bits.
Module Instance Base Address Register Address
l3regs 0xFF800000 0xFF800000

Offset: 0x0

Access: WO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

lwhps2fpga

WO 0x0

hps2fpga

WO 0x0

Reserved

nonmpuzero

WO 0x0

mpuzero

WO 0x0

remap Fields

Bit Name Description Access Reset
4 lwhps2fpga

Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or not.

Value Description
0x0 The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master.
0x1 The LWHPS2FPGA AXI Bridge is visible to L3 masters.
WO 0x0
3 hps2fpga

Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not.

Value Description
0x0 The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master.
0x1 The HPS2FPGA AXI Bridge is visible to L3 masters.
WO 0x0
1 nonmpuzero

Controls the mapping of address 0x0 for L3 masters other than the MPU. Determines whether address 0x0 for these masters is mapped to the SDRAM or on-chip RAM. Only affects the following masters: DMA controllers (standalone and those built in to peripherals), FPGA-to-HPS Bridge, and DAP.

Value Description
0x0 Maps the SDRAM to address 0x0 for the non-MPU L3 masters.
0x1 Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 masters independent of this field's value.
WO 0x0
0 mpuzero

Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or On-chip RAM. This field only has an effect on the MPU L3 master.

Value Description
0x0 Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM is also always mapped to address 0xfffd_0000 for the MPU L3 master independent of this field's value.
0x1 Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the MPU L3 master independent of this field's value.
WO 0x0