LWHPS2FPGA AXI Bridge Module Summary

Registers in the LWHPS2FPGA AXI Bridge Module.

Base Address: 0xFF400000

Register Address Offset	Bit Fields
`ID Register Group`
`periph_id_4` `0x1FD0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`periph_id_4` `RO 0x4`
`periph_id_0` `0x1FE0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`pn7to0` `RO 0x1`
`periph_id_1` `0x1FE4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`jep3to0_pn11to8` `RO 0xB3`
`periph_id_2` `0x1FE8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rev_jepcode_jep6to4` `RO 0x6B`
`periph_id_3` `0x1FEC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rev_and` `RO 0x0`				`cust_mod_num` `RO 0x0`
`comp_id_0` `0x1FF0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`preamble` `RO 0xD`
`comp_id_1` `0x1FF4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`genipcompcls_preamble` `RO 0xF0`
`comp_id_2` `0x1FF8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`preamble` `RO 0x5`
`comp_id_3` `0x1FFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`preamble` `RO 0xB1`
`Master Register Group`
`FPGA2HPS AXI Bridge Registers`
`fn_mod_bm_iss` `0x2008`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`wr` `RW 0x0`	`rd` `RW 0x0`
`ahb_cntl` `0x2044`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`force_incr` `RW 0x0`	`decerr_en` `RW 0x0`
`HPS2FPGA AXI Bridge Registers`
`fn_mod_bm_iss` `0x3008`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`wr` `RW 0x0`	`rd` `RW 0x0`
`ahb_cntl` `0x3044`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`force_incr` `RW 0x0`	`decerr_en` `RW 0x0`
`32-bit Master`
`fn_mod_bm_iss` `0x5008`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`wr` `RW 0x0`	`rd` `RW 0x0`
`wr_tidemark` `0x5040`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`level` `RW 0x4`
`fn_mod` `0x5108`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`wr` `RW 0x0`	`rd` `RW 0x0`
`Slave Register Group`
`L3 Slave Register Group`
`fn_mod` `0x45108`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`wr` `RW 0x0`	`rd` `RW 0x0`