mpumodrst
Module Instance | Base Address | Register Address |
---|---|---|
rstmgr | 0xFFD05000 | 0xFFD05010 |
Offset: 0x10
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
l2 RW 0x0 |
scuper RW 0x0 |
wds RW 0x0 |
cpu1 RW 0x1 |
cpu0 RW 0x0 |
mpumodrst Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
4 | l2 | Resets L2 cache controller |
RW | 0x0 |
3 | scuper | Resets SCU and peripherals. Peripherals consist of the interrupt controller, global timer, both per-CPU private timers, and both per-CPU watchdogs (except for the Watchdog Reset Status registers). |
RW | 0x0 |
2 | wds | Resets both per-CPU Watchdog Reset Status registers in MPU. |
RW | 0x0 |
1 | cpu1 | Resets Cortex-A9 CPU1 in MPU. It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until software is ready to release CPU1 from reset by writing 0 to this field. On single-core devices, writes to this field are ignored.On dual-core devices, writes to this field trigger the same sequence as writes to the CPU0 field (except the sequence is performed on CPU1). |
RW | 0x1 |
0 | cpu0 | Resets Cortex-A9 CPU0 in MPU. When software changes this field from 0 to 1, it triggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted. When software changes this field from 1 to 0, it triggers the following sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de-asserted. Software needs to wait for at least 64 osc1_clk cycles between each change of this field to keep the proper reset/clkoff sequence. |
RW | 0x0 |