ctrl

If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master is pending. Hardware leaves the ETR stalled until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.

This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ field. A 1 indicates that the ETR has stalled its AXI master

Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect. Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.

This field controls whether the ETR is requested to idle its AXI master interface (i.e. finish outstanding transactions and not initiate any more) to the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager makes a request to the ETR to stall its AXI master and waits for it to finish any outstanding AXI transactions before a warm reset of the L3 Interconnect or a debug reset of the ETR. This stalling is required because the debug logic (including the ETR) is reset on a debug reset and the ETR AXI master is connected to the L3 Interconnect which is reset on a warm reset and these resets can happen independently.

This is the acknowlege (high active) that the FPGA handshake acknowledge has been received by Reset Manager.

Software writes this field 1 to initiate handshake request to FPGA . Software waits for the FPGAHSACK to be active and then writes this field to 0. Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in this case.

This field controls whether to perform handshake with FPGA before asserting warm reset. If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm reset signals. However if FPGA is already in warm reset state, the handshake is not performed. If set to 0, the handshake is not performed

This is the acknowlege (high active) that the SCAN manager has successfully idled its output clocks.

Software writes this field 1 to request to the SCAN manager to idle its output clocks. Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. its input clock is disabled) so software should timeout in this case.

Enables a handshake between the Reset Manager and Scan Manager before a warm reset. The handshake is used to warn the Scan Manager that a warm reset it coming so it can prepare for it. When the Scan Manager receives a warm reset handshake, the Scan Manager drives its output clocks to a quiescent state to avoid glitches. If set to 1, the Reset Manager makes a request to the Scan Managerbefore asserting warm reset signals. However if the Scan Manager is already in warm reset, the handshake is skipped. If set to 0, the handshake is skipped.

This is the acknowlege (high active) that the FPGA manager has successfully idled its output clock.

Software writes this field 1 to request to the FPGA Manager to idle its output clock. Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so software should timeout in this case.

Enables a handshake between the Reset Manager and FPGA Manager before a warm reset. The handshake is used to warn the FPGA Manager that a warm reset it coming so it can prepare for it. When the FPGA Manager receives a warm reset handshake, the FPGA Manager drives its output clock to a quiescent state to avoid glitches. If set to 1, the Manager makes a request to the FPGA Managerbefore asserting warm reset signals. However if the FPGA Manager is already in warm reset, the handshake is skipped. If set to 0, the handshake is skipped.

This is the acknowlege for a SDRAM self-refresh mode request initiated by the SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put the SDRAM devices into self-refresh mode.

Software writes this field 1 to request to the SDRAM Controller Subsystem that it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM contents across a software warm reset. Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. Note that it is possible for the SDRAM Controller Subsystem to never assert SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.

This field controls whether the contents of SDRAM devices survive a hardware sequenced warm reset. If set to 1, the Reset Manager makes a request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before asserting warm reset signals. However, if SDRAM is already in warm reset, Handshake with SDRAM is not performed.

This is a one-shot bit written by software to 1 to trigger a hardware sequenced warm reset. It always reads the value 0.

This is a one-shot bit written by software to 1 to trigger a cold reset. It always reads the value 0.