GPLMUX53

Selection between GPIO and LoanIO output and output enable for GPIO53 and LoanIO53. These signals drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.

Module Instance	Base Address	Register Address
`sysmgr`	`0xFFD08000`	`0xFFD086A8`

Offset: 0x6A8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`sel` `RW 0x0`

GPLMUX53 Fields

Bit	Name	Description	Access	Reset
0	`sel`	Select source for GPIO/LoanIO 53. 0 : LoanIO 53 controls GPIO/LOANIO[53] output and output enable signals. 1 : GPIO 53 controls GPIO/LOANI[53] output and output enable signals.	`RW`	`0x0`