dr

         The data register is a 16-bit read/write buffer for the
transmit/receive FIFOs. When the register is read, data in the receive
FIFO buffer is accessed. When it is written to, data are moved into the
transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are
reset when SSI_EN = 0.Note that the data register occupies thirty-six 32-bit 
address locations of the memory map to facilitate burst transfers. 
Writing to any of these address locations has the same effect as pushing the data from 
the bus into the TxFIFO and reading from any of these location has the same effect as 
popping data from the RxFIFO onto the bus.
Module Instance Base Address Register Address
i_spis_0_spis 0xFFDA2000 0xFFDA2060 to 0xFFDA20EC
i_spis_1_spis 0xFFDA3000 0xFFDA3060 to 0xFFDA30EC

Offset: 0x60 to 0xEC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

dr

RW 0x0

dr Fields

Bit Name Description Access Reset
15:0 dr 
Data Register.
When writing to this register, you must right-justify the data. Read
data are automatically right-justified.
Read = Receive FIFO buffer
Write = Transmit FIFO buffer
 RW 0x0