icr
Interrupt Clear Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spis_0_spis | 0xFFDA2000 | 0xFFDA2048 |
| i_spis_1_spis | 0xFFDA3000 | 0xFFDA3048 |
Offset: 0x48
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
icr RO 0x0 |
||||||||||||||
icr Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | icr | Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts. Writing to this register has no effect. |
RO | 0x0 |