fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth

Module Instance	Base Address	Register Address
`i_noc_mpu_m0_fpga2sdram0_axi128_I_main_QosGenerator`	`0xFFD16780`	`0xFFD16790`

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`BANDWIDTH` `RW 0xC80`

fpga2sdram0_axi128_I_main_QosGenerator_Bandwidth Fields

Bit	Name	Description	Access	Reset
12:0	`BANDWIDTH`	In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold is in units of 1/256th bytes per cycle. The formula to calculate this value is: `Bandwidth = Throughput (Mbsp) * 256 / Clock Frequency`. For example, 80 MBps on a 250 MHz interface has the value 0x0052 (`BW = 80Mbps * 256/ 250MHz = 81.92`, which is rounded to 0x0052).	`RW`	`0xC80`

Bit

Name

Description

Access

Reset

12:0

BANDWIDTH

In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold is in units of 1/256th bytes per cycle. The formula to calculate this value is: Bandwidth = Throughput (Mbsp) * 256 / Clock Frequency. For example, 80 MBps on a 250 MHz interface has the value 0x0052 (BW = 80Mbps * 256/ 250MHz = 81.92, which is rounded to 0x0052).

RW

0xC80