fpga2sdram0_axi128_I_main_QosGenerator_Mode

         
      
Module Instance Base Address Register Address
i_noc_mpu_m0_fpga2sdram0_axi128_I_main_QosGenerator 0xFFD16780 0xFFD1678C

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

MODE

RW 0x3

fpga2sdram0_axi128_I_main_QosGenerator_Mode Fields

Bit Name Description Access Reset
1:0 MODE
0 = Programmable mode: a programmed priority is assigned to each read or write, 1 = Bandwidth Limiter Mode: a hard limit restricts throughput, 2 = Bypass mode: (<See SoC-specific QoS generator documentation>), 3 = Bandwidth Regulator mode: priority decreases when throughput exceeds a threshold.
RW 0x3