fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_noc_mpu_m0_fpga2sdram0_axi128_I_main_QosGenerator | 0xFFD16780 | 0xFFD16780 |
Offset: 0x0
Access: RO
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CORECHECKSUM RO 0x721F8 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CORECHECKSUM RO 0x721F8 |
CORETYPEID RO 0x4 |
||||||||||||||
fpga2sdram0_axi128_I_main_QosGenerator_Id_CoreId Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:8 | CORECHECKSUM | Field containing a checksum of the parameters of the IP. |
RO | 0x721F8 |
| 7:0 | CORETYPEID | Field identifying the type of IP. |
RO | 0x4 |