fpga2soc_axi128_I_main_QosGenerator_Id_RevisionId
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_noc_mpu_m0_fpga2soc_axi128_I_main_QosGenerator | 0xFFD16200 | 0xFFD16204 |
Offset: 0x4
Access: RO
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLEXNOCID RO 0x129FF |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLEXNOCID RO 0x129FF |
USERID RO 0x0 |
||||||||||||||
fpga2soc_axi128_I_main_QosGenerator_Id_RevisionId Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:8 | FLEXNOCID | Field containing the build revision of the software used to generate the IP HDL code. |
RO | 0x129FF |
| 7:0 | USERID | Field containing a user defined value, not used anywhere inside the IP itself. |
RO | 0x0 |