lwsoc2fpga

         Per-Master Security bit for Lightweight SOC2FPGA
Module Instance Base Address Register Address
noc_fw_soc2fpga_soc2fpga_scr 0xFFD13500 0xFFD13500

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

etr

RW 0x0

ahb_ap

RW 0x0

nand

RW 0x0

sdmmc

RW 0x0

usb1

RW 0x0

usb0

RW 0x0

emac2

RW 0x0

emac1

RW 0x0

emac0

RW 0x0

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dma

RW 0x0

Reserved

mpu_m0

RW 0x0

lwsoc2fpga Fields

Bit Name Description Access Reset
25 etr 
Security bit configuration for transactions from etr to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
24 ahb_ap 
Security bit configuration for transactions from ahb_ap to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
23 nand 
Security bit configuration for transactions from nand to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
22 sdmmc 
Security bit configuration for transactions from sdmmc to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
21 usb1 
Security bit configuration for transactions from usb1 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
20 usb0 
Security bit configuration for transactions from usb0 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
19 emac2 
Security bit configuration for transactions from emac2 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
18 emac1 
Security bit configuration for transactions from emac1 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
17 emac0 
Security bit configuration for transactions from emac0 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
8 dma 
Security bit configuration for transactions from dma to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
0 mpu_m0 
Security bit configuration for transactions from mpu0 to lwsoc2fpga. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0